Research Profile for Koufopavlou Odysseas

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VLSI Laboratory
Department of Electrical and Computer Engineering
Research Activity
networks, computer architecture and communications, VLSI Design, security
His research interests include computer networks, high performance communication subsystems architecture and implementation, VLSI low power design, and VLSI crypto systems.
Research Infrastructure
Costas E. Goutis, Professor, Director of VLSI Lab

Odysseas Koufopavlou, Professor

Vassilis Paliouras, Assistant Professor
Dell PowerEdge900 server: a sixteen-core machine with 64GB RAM, running 64-bit Red Hat Enterprise Linux (RHEL 5) and
Large number of PC workstations running windows and linux.
State-of-the-art equipment for testing and digital design debugging: Tektronix TLA7000 Logic analyzer, 68 channels, 8 GHz MagniVu Timing, 450 MHz State Clock equipped with FS2 FPGAVIEW, TLA support for XILINX FPGAS. PGA3 300MHz pattern generator.
Complete set of tools available via Europractice to support all aspects of electronic design, including HDL model development, synthesis, simulation and verification, timing analysis, power analysis, place and route. In particular, the available infrastructure includes

Full Mentor Graphics suite (28 seats): Complete set of tools for all design procedures ranging from system-level HDL specification to back-end IC development support

Full Cadence IC design flow, including HDL-based front-end tools to IC back-end tools

Synopsys front-end for HDL modeling, synthesis, timing and power analysis and optimization tools.

Xilinx tools for FPGA prototyping of embedded systems and ASICs: ISE Foundation, XST synthesis, IMPACT for binary file generation, ILA (Integrated and Logic Analyzer) and Chipscope Pro for FPGA debugging.

Model-based system design flows based on Matlab, Simulink from Mathworks and SystemGenerator from Xilinx.

A large number of development boards and kits based on Spartan 3E, Virtex-4 and Virtex-5 devices. The particular boards target embedded system, DSP and ASIC prototyping.

Software tools for architecture exploration and compiler optimizations.
Research Activities
•VITAL++ (ICT-224287) ): “Embedding P2P technology in Next Generation Networks: A New Communication Paradigm & Experimentation Infrastructure ”
•PII (ICT-224119): “Pan-European Laboratory Infrastructure Implementation”
•AUTOI (ICT-216404) ): “Autonomic Internet”
•Phosphorus (IST-034115-IP): “Lambda User Controlled Infrastructure for European Research”
•VITAL (IST-034284-STP): “Enabling Convergence of IP Multimedia Services over Next Generation Networks Technology”
•Πόλος Καινοτομίας Δυτικής Ελλάδας: “Σύστημα Παροχής Αλληλεπιδραστικών Υπηρεσιών Εξυπηρέτησης Πολιτών”
•IST-FLEXINET: “Flexible Network and Gateways Architecture for Enhanced Access Network Services and Applications”
•ΠΕΠΕΡ: "Συστημα Bluetooth Χαμηλής Κατανάλωσης Ισχύος"
Selimis, G.N., Fournaris, A.P., Michail, H.E., Koufopavlou, O.,"Improved throughput bit-serial multiplier for GF(2m) fields", Integration, the VLSI Journal, vo. 42, no. 2, pp. 217-226, February 2009.
Chrysoulas, C., Haleplidis, E., Kostopoulos, G., Haas, R., Koufopavlou, O.,"Towards a resource management and service deployment framework”. International Journal of Network Management, vo. 18, no. 4, pp. 345-363, July 2008.
Fournaris, A.P., Koufopavlou, O.,"Versatile multiplier architectures in GF (2k) fields using the Montgomery multiplication algorithm", Integration, the VLSI Journal, vo. 41, no. 3, pp. 371-384, May 2008.
Chrysoulas, C., Haleplidis, E., Kostopoulos, G., Haas, R., Denazis, S., Koufopavlou, O.,"Towards a service-enabled distributed router architecture", IET Circuits, Devices and Systems, vo. 2, no. 1, pp.60-68, February 2008.
Selimis, G., Kakarountas, A., Fournaris, A., Milidonis, A., Koufopavlou, O., " A Low Power Design for SBOX Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users", Journal of Low Power Electronics (JOLPE), vo.3, no. 3, pp. 327-336(10), December 2007.
Fournaris, A.P., Koufopavlou, O., "Applying systolic multiplication-inversion architectures based on modified extended Euclidean algorithm for GF(2k) in elliptic curve cryptography", Computers and Electrical Engineering, vo. 33, no. 5-6,pp.333-348, September 2007.
Kitsos, P., Sklavos, N., Koufopavlou, O., "UMTS security: System architecture and hardware implementation", Wireless Communications and Mobile Computing", vo. 7, no. 4, pp. 483,494, May 2007.
Kitsos, P., Galanis, M.D., Koufopavlou, O., "Architectures and FPGA implementations of the 64-bit misty1 block cipher", Journal of Circuits, Systems and Computers", vo. 15, no. 6, pp. 817-831, December 2006.
Tychopoulos, A., Papagiannakis, I., Klonidis, D., Tzanakaki, A., Kikidis, J., Koufopavlou, O., Tomkos, I., "A low-cost inband FEC scheme for SONET/SDH optical metro networks, IEEE Photonics Technology Letters, vo. 18, no. 24, pp.2581- 2583, November 2006.
Tychopoulos, A., Koufopavlou, O., Tomkos, I., "FEC in optical communications - A tutorial overview on the evolution of architectures and the future prospects of outband and inband FEC for optical communications", IEEE Circuits and Devices Magazine, vo. 22, no. 6, pp.79-86, November 2006.
Sklavos, N., Kitsos, P., Papadopoulos, K., Koufopavlou, O., "Design, architecture and performance evaluation of the wireless transport layer security", Journal of Supercomputing, no. 36, vo. 1, pp. 33-50, April 2006.
Sklavos, N., Koufopavlou, O., “On the Hardware Implementation of RIPEMD Family Processor: Networking High Speed Hashing, up to 2 Gbps”, Computers and Electrical Engineering Journal, vo. 31, no. 6, pp. 361 - 379, September 2005.
Sklavos, N., Koufopavlou, O. "Access Control in Networks Hierarchy: Implementation of Key Management Protocol", International Journal of Network Security, vo. 1, no. 2, pp. 103 - 109, September 2005.
Kitsos, P., Galanis, M., Koufopavlou, O., "An FPGA Implementation of the GPRS Encryption Algorithm 3 (GEA3)", Journal of Circuits, Systems, and Computers (JCSC), vo. 14, no. 2, pp. 217 - 231, June 2005.
Moldovyan, N. A., Moldovyan, A. A.,Sklavos, N., Koufopavlou, O. "CHESS-64, A Block Cipher Based on Data-Depended Operations Design Variants and hardware Implementation Efficiency", Asian Journal of Information Technology (AJIT), vo. 4, no. 4, pp. 323 - 334, March 2005.
Alcatel Germany
IBM Switzerland
E-codes Greece
Dynacomp Greece
WIT Ireland
Telekom Austria
Fraunhofer - Focus Germany
RBB Gremanay
Voiceglobe Belgium
Telefonica Spain
BCT Greece

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